The purpose of this workshop is to bring ATE, DFT/BIST, and EDA tools researchers and practitioners together to discuss where the best trade-offs are for economic test of today’s integrated circuits. The arrival of SOC technology has the potential of making test cost via traditional ATE methods prohibitive.
This workshop should provide the ideal forum to engage discussion on this critical topic for the new millennium.
The TRP workshop will start building this overlapping domain and its corresponding new community.