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| Expected
Results |
The research
project will provide the specification and a prototype implementation
of a test access mechanism (TAM) able to complement the IEEE
P1500 standard in defining a comprehensive test strategy for
SoC designs. The TAM will be able to deal with different types
of cores, and to support a hierarchical design paradigm, where
a today SoC might tomorrow be used as an IP core in a more
complex SoC. The definition of the TAM has also to allow a
programmable scheduling of the test operations, so that to
control the power consumption of the chip during the test
execution. This part of the research will have a very significant
industrial impact, because it will provide test engineers
an innovative methodology to design very effective system-level
test strategies while reducing the test developing time and
therefore cost.
In this scenario, reusability-driven, performance, and cost
constraints, the use of built-in self-test (BIST) architectures,
which embed on-chip the test generation and check logic, is
more practical and cost-effective. Nevertheless, new BIST
solutions still need to be defined to keep the area overhead
of the test architecture as low as possible. This is particularly
true for FPGAs, i.e., fully on-chip programmable digital devices,
that it has recently been announced and will soon appear as
embedded cores in SoCs. Despite their next appearance in SoCs,
an effective FPGA BIST methodology has not been defined yet.
This methodology must take into account the final configuration
and must be easily reusable in different designs. The research
wants therefore to give a significant scientific and industrial
contribution in defining innovative, low-cost, and compact
BIST architectures for embedded FPGAs.
Moreover, since power consumption during BIST is, in general,
greater than in normal operating modes BIST techniques, techniques
to deal with power and energy budgeting problems during test
have recently attracted increasing research interest. This
is particularly true in the field of portable electronic equipment
as cellular phones and laptop PCs, with their problems of
battery charge and life.
In this research the participants will address the problem
of defining low power techniques for BIST and diagnosis (BIST/D)
in SoCs using both the already embedded programmable logic
devices and general purpose components, as microprocessors.
When dealing with SoCs, there is then the difficulty of repairing
a chip-embedded component both after manufacturing and even
during its field operations. In the past, repairs have usually
been performed mainly on memory chips, typically using fuse-blow
with external laser equipment, and mostly at the manufacturing
level, only. Nevertheless, the capability of repairing a component
after manufacturing and in-field can significantly affect
both the production yield, and the product availability and
dependability after its deployment. To be applicable after
deployment (i.e., at the user-level), the repair strategy
has not to rely on external equipments, but has to be embedded
into the chip, in what is usually referred to as a built-in
self-repair (BISR) architecture.
The research will address the problem of defining new BISR
solutions for memories, microprocessors, and mixed-signal
devices, since their reliability is usually very tightly related
with the reliability of the overall system. The development
of BISR architectures will enrich the area of commercial applications
in which high availability and serviceability is needed, such
as biomedical devices or automotive applications. |
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