|
|
 |
|
|
| Partners'
roles |
| The main objective
of this research is the definition of new Design for Testability
(DfT), Built-In
Self-Test (BIST), and Built-In Self-Repair (BISR) techniques
to improve the quality and
dependability of System-on-Chips (SoCs). Therefore, the network
set up to achieve these
goals groups partners with high scientific and industrial
expertise in the field of SoC design.
The team from Politecnico di Torino has been scientifically
very active for many years in the
field of high-level test structures, BIST, and more recently
BISR architectures. In order to
face the problem from a more general point of view, the network
includes the UPC team that
demonstrated for many years to be a center of excellence in
the field of Low Power and
mixed-signal test related issues. Given the new trend of embedding
programmable devices
into complex SoCs, the network will fruit of the work of the
UMII-CNRS team, which is one of
the European leaders in the field of FPGA testing. The high
interaction guaranteed by the
project organization, will allow to share knowledge and solutions
in order to address the
problem of SoC testing from an effective and comprehensive
point of view. The three
industrial partners are world leaders in telecom applications
(SIEMENS ICN), in IP core
development (Virage Logic) and in BIST insertion tools (LogicVision),
respectively. In the
current project, they will play a double role: from one hand
they will technically contribute to
the development of several tasks and, on the other hand, they
will guarantee a continuous
monitoring of the project activities, to keep the work focused
on real industrial needs.
|
|
|