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| Scenario |
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Thanks to the swift advance of semiconductor technology,
companies’ can and continually do introduce products with
more functions, higher reliability, lower costs, and at
short intervals. Integrated circuits (ICs) are now so cheap
that industries now live off integrating even more functions
into even smaller packages, even to creating entire Systems-on-Chip
Arguably, some success of the economy-at-large for at least
the next decade hinges on the speed with which complex new
chips, and the products using them, not only can be developed
and manufactured, but also have their performance tested,
diagnosed, and verified. At some point, 100-million-transistor
chips are expected to emerge. But before then, as the National
Technology Roadmap for Semiconductors spelled out in 1997,
major hurdles must be overcome, some of which are related
to test technology. Different solutions are possible, but
the goal they share is to ensure that the test methods contribute
to the growth of the semiconductor industry and do not slow
it down. On the thorny road to the fabrication of more and
more integrated and fast chips, semiconductor technology
will challenge test engineers as never before. Complexities,
performances, and densities, not to mention cost, will all
increase. To keep these scaling trends going, IC realization
methods are expected to change fundamentally, directly affecting
the test methods, tools, and equipment adopted. Otherwise,
100-million-transistor chips will not be adequately tested,
debugged, diagnosed, measured, or even sometimes repaired,
thus affecting the quality and the reliability of the global
end-products. All four scaling trends have implications
for test: every one of them challenges present ability to
efficiently create new products. It is not sufficient to
address just one of the challenges: all must be dealt with
at the same time. Progressively greater IC complexity raises
several new problems. One of them is the bandwidth gap between
a chip’s internal performance and the output capability
of its package pins. This problem steadily reduces the accessibility
of transistors from chip pins, which could be a big problem
for IC testing. Moreover, the growing disparity between
internal clock frequencies and the output capabilities of
the I/Os makes at-speed testing of IC performance extremely
difficult, if not impossible. The widening gap between external
and internal bandwidth is the main reason why processors
and dynamic memories are now being integrated into the same
chip. System-on-Chip (SoC) design based on embedded cores
implies reuse of previously designed complex functional
blocks, a.k.a. intellectual property (IP) blocks. These
cores may have varying degrees of readiness for reuse in
SoC design, may stem from varied sources, and are designed
for use in a multiplicity of diverse SoCs. Nevertheless,
they must be able to anticipate the desired SoC test constraints
for all the possible target SoC designs. The SoC integration
task would be simpler if core designs were more test-friendly,
and SoC designers would have more flexibility in choosing
the best overall test methodologies for their chips. Consequently,
the IEEE P1500 standard for embedded-core test is under
development. Its goal is to ensure test-friendliness and
interoperability of cores from diverse sources. But instead
of standardizing cores internal test methods or chip-level
test access scheme and configuration, it concentrates on
a standardized, but configurable and scalable, core test
interface or wrapper. This wrapper must allow easy test
access to the core in a system chip design, interfacing
with an on-chip test access mechanism (TAM), whose task
is mainly to manage the execution of the test of the overall
chip. The definition of a standard TAM is nevertheless out
of the current scope of P1500.
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