FEATURES
Publications
All TestGroup publications are available through PORTO, the Open Repository of publications produced by the scientific community of Politecnico di Torino.
Funded project
We are involved in several national and international collaborative research projects co-funded by the European Commission or by national research fundings.
Partners
We actively collaborate with international academic and industrial partners. Learn more about companies and research institutions collaborating with us.
Tools and downloads
As computer scientists we are highly committed to Open Source. Most of our developed code is released under Open Source licenses and is available on this website for free download.
About
TestGroup is one of the leading European research and development teams in the field of System Design, Testing and Reliability.
Our vision
Researching into new challenging problems to deliver breakthrough solutions for testing, reliability and security of next generation electronic systems.
Our mission
Understand the needs and requirements of future technologies.
Deliver superior technical capabilities.
Demonstrate increasing value.
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Build reliable systems with reduced overhead.
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Innovative solutions for hardware security.
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Hardware reconfigurable systems for high-performance and safety critical systems.
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Test solutions to deliver high-quality digital systems, with focus on memory technologies.
OUR TEAM
PAOLO PRINETTO
Stefano Di Carlo
Alessandro Savino
Alessandro Vallero
Alberto Carelli
Andrea Romanelli
Stefano Sclaverano
Former members
Latest posts
Hiring 15 PhD students in Europe in the field of Approximate Computing
APROPOS) project is hiring 15 international “Early Stage Researchers” for PhD positions in Europe (Finland, Sweden, Netherlands, Austria, Switzerland, Italy, France, Spain, and UK) with 36-month fully-funded contracts.
Testgroup @ HiPEAC CSW 2019
TestGroup team is attending HiPEAC Computing Systems Week 2019 in Bilbao (Spain). Interesting technical discussions and presentations, lot of friends and colleagues, all organized in a beautiful landscape.
Probabilistic estimation of the application-level impact of precision scaling in approximate computing applications @ Microelectronics Reliability Journal
Good news for our research group !!!!
The article “Probabilistic estimation of the application-level impact of precision scaling in approximate computing applications” has been published on the Microelectronics Reliability Journal and is now available online”.
Paper accepted @ DFTS 2019
On behalf of the DFT19 Program Committee, we are delighted to inform you that your paper “Combining Cluster Sampling and ACE analysis to improve fault-injection based reliability evaluation of GPU-based systems” has been ACCEPTED for ORAL presentation at the 32th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
Invited talk @ 25th IEEE International Symposium on On-Line Testing and Robust System Design
Today at 5:15PM I’m going to give an invited talk at the 25th IEEE International Symposium on On-Line Testing and Robust System Design in Kazan in Rhodes (Greece).
The topic of the talk will be “Bayesian Models For Early Cross-Layer Reliability Analysis and Design Space Exploration” and will be part of Session 5S “Cost-Effective Resilience: Advanced Cross-Layer Analysis and Optimization Techniques” organized by Prof. M. Shafique (TU Wien).
Invited Talk Presentation @ AxC 2019
Our Assistant Professor Alessandro Savino is going to give a presentation on Friday, March 29th at the Forth Workshop on Approximate Computing 2019 – AxC’19, one of the Workshops of the DATE 2019
SyRA Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems @ IEEE Transactions on Computer
After more than 1 year from its end, the FP7 Clereco project (http://www.clereco.eu) still produces results in the field of cross-layer reliability analysis.
This paper that has been accepted for publication in an upcoming issue of IEEE Transactions on Computers proposes a framework for Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
Keynote talk @ 16th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM
Today I’m going to give a keynote talk at the 16th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM in Kazan (Russia).
The topic of the talk will be “Cross Layer Reliability: a Reality or a Promise Never Coming True?”.
Shielding Performance Monitor Counters: a double edge weapon for safety and security
Dr. Alessandro Vallero from TestGroup presented our latest study on “Multi-faceted Microarchitecture Level Reliability Characterization for NVIDIA and AMD GPUs” @ 2018 IEEE VLSI Test Symposium, San Francisco, CA, USA (April 22-25, 2018).
Testgroup @ IOLTS 2018
TestGroup team is attending IOLTS 2018 in Platja D’Aro (Spain). Interesting technical discussions and presentations, lot of friends and colleagues, all organized in a beautiful landscape …