All TestGroup publications are available through PORTO, the Open Repository of publications produced by the scientific community of Politecnico di Torino.
We are involved in several national and international collaborative research projects co-funded by the European Commission or by national research fundings.
We actively collaborate with international academic and industrial partners. Learn more about companies and research institutions collaborating with us.
Tools and downloads
As computer scientists we are highly committed to Open Source. Most of our developed code is released under Open Source licenses and is available on this website for free download.
TestGroup is one of the leading European research and development teams in the field of System Design, Testing and Reliability.
Researching into new challenging problems to deliver breakthrough solutions for testing, reliability and security of next generation electronic systems.
Understand the needs and requirements of future technologies.
Deliver superior technical capabilities.
Demonstrate increasing value.
Build reliable systems with reduced overhead.
Innovative solutions for hardware security.
Hardware reconfigurable systems for high-performance and safety critical systems.
Test solutions to deliver high-quality digital systems, with focus on memory technologies.
Stefano Di Carlo
Giuseppe Airò Farulla
Several people have contributed to build our group as it is today.
Without the support of strongly motivated MS / Ph.D. students and Post. Docs we would not have been able to achieve the results we reached over the years. Several of our former colleagues built an outstanding career either in other universities or top level enterprises. Read more
Sakis Chatzidimitriou Ph.D. student at University of Athens under Prof. Dimitris Gizopoulos presented yesterday the CPUs fault injection study (on ARM Cortex-A9 CPU) between microarchitecture-level and RT-level result of a collaboration between University of Athens, Politecnico di Torino and Intel/Yogitech in CLERECO FP7 project.
I’m very proud to announce that yesterday my student Alessandro Vallero defended his Ph.D. thesis in front of a committee of five experts in his research field and was awarded the Ph.D. degree in Computer Engineering “cum laude”,
On May 30 Alessandro VALLERO will discuss his PhD thesis, titled ” Cross layer reliability estimation for digital systems”
The 22nd IEEE European Test Symposium will start in a few days in Limassol (Cyprus).
Testgroup will be there with two interesting presentations.
STT-MRAM model for CACTI simulator
We are happy to announce that HiPEACinfo vol. 50 is now available for download from the HiPEAC website (https://www.hipeac.net/assets/public/publications/newsletter/hipeacinfo50.pdf). It contains an nice overview of the Clereco results. If you have a LinkedIn account, please consider posting about your article and sharing the link to the magazine via LinkedIn.
New paper titled “SIFI a reliability evaluation framework for soft-errors built on top of Multi2Sim” accepted for publication at the 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS’17), July 3-5, 2017 in Thessaloniki, Greece.
New paper titled “RT Level vs. Microarchitecture Level Reliability Assessment: Case Study on ARM Cortex-A9 CPU” accepted for publication at the 47th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2017), June 26-29, 2017 in Denver, CO (USA).
On April 24th my Ph.D. student Alessandro Vallero will attend ISPASS 2017 in Santa Rosa, CA to present our latest paper: Microarchitecture Level Reliability Comparison of Modern GPU Designs: first findings..
Concluded in Autumn 2016, the EU-funded CLERECO (Cross Layer Early Reliability Evaluation for the Computing cOntinuum) project proposed a scalable, cross-layer methodology and supporting suite of tools for accurate and fast estimations of computing systems’ reliability.