Vendor Session Presentations
Session 7B – Wednesday May 29th
Moderator: Hans Manhaeve – Ridgetop Europe
Time: 9:15
Title: Test and Repair for SoC Memories and Hierarchical Test for AMS & PHY IP
Presenter: Yervant Zorian, Synopsys Fellow
Abstract:
Memory test and repair at 7nm and smaller technologies present new and unique challenges to SoC and DFT designers. With growing process variation and complexity, SoC designers need to overcome new memory fault types (specific to FinFET) to offer high test coverage while satisfying performance and reliability needs specific to new applications like Artificial Intelligence, Machine Learning and Automotive.
This tutorial will introduce the next generation of STAR Memory System, Synopsys’ memory test and repair solution including details of the recently announced support for embedded MRAM (eMRAM) technology. The speaker will also discuss the DesignWare STAR Hierarchical System, a hierarchical test and diagnostics solution for all analog/mixed signal IP/cores on your SoC. The tutorial will cover test, repair, diagnostics as well as in-field self-test capabilities with examples of successful customer case studies.
Time: 9:45
Title: Advantest and EDA: Partnering to Deliver Customer Values
Presenter: Michael Braun, Advantest
Abstract:
Today’s economy and entire society rest upon the dependability of information technology and especially of the underlying hardware infrastructure. Thoroughly tested systems are hence mandatory for a responsible use of todays and future technologies. However, semiconductor test is becoming increasingly challenging, since recent technology advances lead to systems of tremendous complexity in various aspects.
Advantest, as one of the leading providers for semiconductor test solutions, is committed to provide answers to these challenges. As also identified in our Grand Design plan, we are driving a holistic vision of the future of semiconductor test and reliability together with our academic and industrial partner network. During the talk, we will present joint developments with the EDA industry.
Session 11B – Thursday May 30th
Moderator: Pete Harrod – ARM
Time: 9:15 – Mini-Tutorial
Title: The (black) art of current test
Presenter: Hans Manhaeve, CEO Ridgetop Europe
Abstract
This tutorial aims to make up a state of the art regarding the application of current based test methodologies, will reflect on whether or not the IDDQ sun has set and will review on how current based tests (IDDQ, ISSQ, IDDT) test, related DFT, test preparations (ATPG) and execution and decision-making strategies can help to reduce test cost, shorten time to market and meanwhile improve product quality in the scope of creating nano-scale devices with giga-scale or mixed signal complexity in a competitive environment where the market is asking for the best quality and reliability levels at the lowest cost.
Session 12B – Thursday May 30th
Moderator: Juergen Schloeffel – Mentor, a Siemens Business
Time11:00
Title: Moving DFT solutions to the next level
Presenter: Kan Thapar (Mentor, a Siemens Business)
Abstract:
As technology advances and the problems being solved become bigger, there is a general need to move the user interface up a level of abstraction with more automation and to improve tool capabilities down to a more precise level of fidelity. This is especially true for semiconductor devices and DFT. Many SoCs are more complex than entire subsystems were just several years ago. Design teams face a daunting challenge to develop a complete design within a short design schedule. It is not possible to perform DFT by implementing discrete DFT functions one at a time and leave it to the user to manage and integrate them together and to access and operate individual blocks in a modern SoC. Instead, DFT EDA tools are now built as one piece of code and data base with a plug-and-play hierarchical infrastructure. This allows the tools to manage the various DFT functions and porting block DFT logic and patterns through the hierarchical design seamlessly. As a result, the user can get more done, quicker, by working at a higher level of abstraction. At the same time as the user works at a higher level, the tools need to work at a much finer level of precision to detect subtle defects that can occur with new fabrication technologies. Automation has also been added for Automotive-grade ATPG to provide such defect detection fidelity and cell-aware diagnosis to precisely identify yield limiting issues.
Time: 11:30
Title: IP Solutions for Functional Safety Applications
Presenter: Pete Harrod, Director of Functional Safety, CPU Group, Arm
Abstract:
In this vendor session, we will discuss some of the requirements placed on IP if it is to be used successfully in functional safety applications. The 2nd edition of ISO 26262 includes a new Part 11 which gives guidance on applying the standard to semiconductors and IP and some aspects of Part 11 will be discussed with reference to some examples of IP developments at Arm. Finally an example will be shown of a functional safety IP product that is intended for the automotive market.
Time: 12:00
Title: ProChek Plus – A solution for Process assessment from a quality/reliability perspective
Presenter: Hans Manhaeve, Ridgetop Europe
Abstract:
This presentation will present the ProChek Plus solution. ProChek Plus is a mini test system dedicated at performing device characterisation and qualification both from a performance as well as from a reliability (BTI, HCI, EM, SM) perspective.
