Technical Program
Monday May 27, 2019 |
Tuesday May 28, 2019 |
Wednesday May 29, 2019 |
Thursday May 30, 2019 |
Friday May 31, 2019 |
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Keynote 2: Shaojun Wei 08:30-09:15 Conference Room 1 |
Keynote 3: Jochen Müller 08:30-09:15 Conference Room 1 |
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Opening 09:00-09:30 Conference Room 1 |
Fringe Workshop TESTA 09:00-15:30 Seminar Room 4 |
Fringe Workshop TruDevice 09:00-10:00 Seminar Room 1 |
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Session 7A Memory 09:15-10:15 Conference Room 1 |
Session 7B Vendor 09:15-10:15 Seminar Room 7/8 |
Session 7C Embedded Workshop 09:15-10:15 Seminar Room 1 |
Session 11A AxC & Neuromorphic 09:15-10:15 Conference Room 1 |
Session 11B Vendor 09:15-10:15 Seminar Room 7/8 |
Session 11C Embedded Tutorial 2 09:15-10:15 Seminar Room 1 |
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Keynote 1: Kaushik Roy 09:30-10:15 Conference Room 1 |
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Fringe Workshop Joint Shiva / TruDevice 10:00-12:15 Seminar Room 1 |
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Coffee & Posters 1 10:15-11:00 Foyer 1st Floor |
Coffee & Posters 2 10:15-11:00 Foyer 1st Floor |
Coffee & Posters 3 10:15-11:00 Foyer 1st Floor |
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Session 2A Security 11:00-12:30 Conference Room 1 |
Session 2B Analog & Mixed Signal Test 11:00-12:30 Seminar Room 1 |
Session 2C ETS2 11:00-12:30 Seminar Room 7/8 |
Session 8A Modeling, Validation & Verification 11:00-12:30 Conference Room 1 |
Special Session 8B Security in Autonomous Systems 11:00-12:30 Seminar Room 7/8 |
Session 8C Embedded Workshop 11:00-12:30 Seminar Room 1 |
Session 12A DfT & BIST for 3D & AMS 11:00-12:30 Conference Room 1 |
Session 12B Vendor 11:00-12:30 Seminar Room 7/8 |
Special Session 12C Dependable Wireless IoT 11:00-12:30 Seminar Room 1 |
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Fringe Workshop Shiva 12:15-18:00 Seminar Room 1 |
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ETS Steering Committee meeting 12:30-14:00 Seminar Room 4 |
Lunch 12:30-14:00 Parkpavillon Ground Floor |
ETS2020 Executive Committee meeting 12:30-14:00 Seminar Room 4 |
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TSS Monday Tutorials Part A |
Special Session 3A Automotive Quality 14:00-15:30 Conference Room 1 |
Session 3B PhD Contest 14:00-15:30 Seminar Room 1 |
Session 9A Panel 14:00-15:30 Conference Room 1 |
Session 9B Embedded Tutorial 1 14:00-15:00 Seminar Room 1 |
Plenary Session 13 Diagnosis 14:00-15:30 Conference Room 1 |
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AMS & RF Test 14:00-16:00 Seminar Room 1 |
System-Level Test 14:00-16:00 Seminar Room 7/8 |
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Coffee and PhD Forum 15:30-16:15 |
Closing 15:30-16:00 Conference Room 1 |
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Coffee Break | ETS Steering Committee meeting 16:00-19:00 Seminar Room 4 |
Fringe Workshop TESTA 16:00-18:00 Seminar Room 4 |
Fringe Workshop TruDevice 16:00-18:00 Seminar Room 1 |
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Session 4A Test Generation 16:15-17:45 Conference Room 1 |
Session 4B Fault Tolerance 16:15-17:45 Seminar Room 1 |
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TSS Monday Tutorials Part B |
Social Event 16:30-22:00 |
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AMS & RF Test 16:30-18:30 Seminar Room 1 |
System-Level Test 16:30-18:30 Seminar Room 7/8 |
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Break 17:45-18:00 |
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Session 5 Wine &Cheese Panel 18:00-19:30 Conference Room 1 |
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Welcome Reception 19:00-21:00 |
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Networking Grill 19:30-21-30 Parkpavillon Ground Floor |
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Date | Time | Event |
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27
Monday
May, 2019
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14:00 – 18:30 |
Tutorial A (Seminar Room 1)
Analog, Mixed-Signal, RF IC Testing: Essentials and Current Trends
Harlampos Stratigopoulos, Sorbonne University – LIP6, FR
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Tutorial B (Seminar Room 7/8)
System-Level Test
Harry Chen, MediaTek, TW
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16:00 – 19:00 |
ETS Steering Committee meeting (Seminar Room 4)
Chair: Matteo Sonza Reorda, Politecnico di Torino, IT
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19:00 – 21:00 |
Welcome Reception
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28
Tuesday
May, 2019
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09:00 – 09:30 |
Opening Session (Conference Room 1)
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09:30 – 10:15 |
Keynote 1 (Conference Room 1)
Cognitive Computing: Design, Verification & Security Challenges
Kaushik Roy, Purdue University, US
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10:15 – 11:00 |
Coffee and Poster Session 1 (Foyer 1st Floor)
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11:00 – 12:30 |
Session 2A – Security (Conference Room 1)
Moderators: Subhasish Mitra, Stanford University, US, and Johanna Sepulveda, TUM, DE
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Session 2B – Analog and Mixed Signal Test (Seminar Room 1)
Moderators: Hans Kerkhoff, University of Twente, NL, and Haralampos Stratigopoulos, Sorbonne University – LIP6, FR
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Session 2C – ETS2: Functional Safety and DFT – Overlap or Conflict? (Seminar Room 7/8)
Moderators: Pete Harrod, ARM, UK, and Zebo Peng, Linkoping University, SE
Presenters:
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12:30 – 14:00 |
Lunch (Parkpavillon Ground Floor)
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ETS Steering Committee meeting (Seminar Room 4)
Chair: Matteo Sonza Reorda, Politecnico di Torino, IT
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14:00 – 15:30 |
Session 3A – Special Session: Maintaining Automotive Quality for Next Generation Microcontrollers (Conference Room 1)
Organizer and Moderator: Daniel Tille, Infineon Technologies, DE
Presenters:
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Session 3B – McCluskey Doctoral Thesis Award Contest – ETS Semi-Finals (Seminar Room 1)
Moderators: Alberto Bosio, École Centrale de Lyon, FR, and Said Hamdioui, TU Delft, NL
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15:30 – 16:15 |
Coffee and PhD Forum (Foyer 1st Floor)
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16:15 – 17:45 |
Session 4A – Test Generation (Conference Room 1)
Moderators: Grzegorz Mrugalski, Mentor, a Siemens Business, PL, and Melanie Schillinsky, NXP, DE
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Session 4B – Fault Tolerance (Seminar Room 1)
Moderators: Valentin Gherman, CEA, FR, and Huang Zhengfeng, Hefei University of Technology, CN
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17:45 – 18:00 |
Break (Room TBD)
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18:00 – 19:30 |
Session 5: Wine and Cheese Panel: Ask the Experts (Conference Room 1)
Organizer and Moderator: Jeff Rearick, AMD, US
We’ll continue our tradition of tapping the collective expertise of the ETS participants by hosting an interactive “Ask The Experts” session during the Wine and Cheese Panel. The twist is that anyone can ask a question and _everyone_ has the chance to be the expert who answers it (or contests the answer of another expert). The general theme is “The Test Industry Roadmap” but anything goes. Prizes will be awarded for best question, best answer, and best rebuttal |
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19:30 – 21:30 |
Networking Grill (Parkpavillon Ground Floor)
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29
Wednesday
May, 2019
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08:30 – 09:15 |
Keynote 2 (Conference Room 1)
Moderator: Krishnendu Chakrabarty, Duke University, US
Software Defined Chips: An Innovative Architecture Leading to Intelligent Computing
Shaojun Wei, Tsinghua University, CN
AbstractIntellectualization is a revolution that human society is experiencing, and it is also the core of the fourth industrial revolution. Obviously it ultimately depends on integrated circuit technology, because not only now, but also in the future for quite a long time, we cannot find other technologies that can replace integrated circuits. Therefore, we have no other options than using integrated circuit technology for implementing intelligence. It is also the reason why people spend a lot of energy focusing on AI chips in the development of artificial intelligence. For a large number of artificial neural networks each of which corresponds to only one application, an integrated circuit that cannot be changed after manufacturing is obviously far from the requirements. Even devices such as FPGA, which are field programmable, can hardly meet the needs of AI development in terms of computing efficiency and energy efficiency. We urgently need to find an innovative chip architecture. This paper will focus on software definition chip (SDC), an innovative chip architecture that allows the chip function to dynamically change in real time with the change of software. SDC moves from traditional software adapting hardware to hardware adapting software. By gradually improving the intelligence of chip, SDC eventually moves to intelligent chip. Besides, the core of SDC is a dynamically reconfigurable PE array that not only has high computing efficiency and energy efficiency, but also improves the reliability of the chip through redundant design, and improve the ability to resist attacks by randomly configuring the space-time position of the sensitive circuits as well. In addition, based on dynamic reconfigurability, the potential security threats caused by test paths in DFT are also mitigated. |
09:15 – 10:15 |
Session 7A – Memory (Conference Room 1)
Moderators: Michele Stucchi, IMEC, BE, and Ioana Vatajelu, TIMA, FR
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Hans Manhaeve, Ridgetop Europe, BE
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Session 7C – Embedded Workshop: Case Studies (Seminar Room 1)
Moderator: Gildas Leger, IMSE-CNM, ES
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10:15 – 11:00 |
Coffee and Poster Session 2 (Foyer 1st Floor)
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11:00 – 12:30 |
Session 8A – Modeling, Validation and Verification (Conference Room 1)
Moderators: Bernd Becker, University of Freiburg, DE, and René Krenz-Baath, Hamm-Lippstadt University of Applied Sciences, DE
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Session 8B – Special Session: Security in Autonomous Systems (Seminar Room 7/8)
Organizer and Moderator: Ilia Polian, University of Stuttgart, DE
Presenters:
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Session 8C – Embedded Workshop: Advances in DfT (Seminar Room 1)
Moderator: Jochen Rivoir, Advantest, DE, Matthias Sauer, Advantest, DE
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12:30 – 14:00 |
Lunch (Room TBD)
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14:00 – 15:30 |
Session 9A – Panel: System-level Test (SLT) – What does the Future Hold? (Conference Room 1)
Organizer: Harry Chen, MediaTek, TW
Panelists:
Summary:Testing of complex electronics-based systems is becoming more difficult and costly. To meet the challenge, can we count on enhanced structural test using advanced fault models such as cell-aware? Or do we have to employ more system-level test (SLT)? Can a more methodical and standardized approach to SLT over current ad hoc practices be developed to achieve better cost efficiency? What about balancing the roles of traditional ATE and SLT testers for a more optimal test flow. Perhaps bring more SLT content upstream to wafer probe or include structural test content as part of in-system test? Is end-to-end test data analytics the solution to closing the diagnostic loop to identify the root causes of field failures? Should we be paying more attention to the role of embedded software when modern complex systems fail? What academic research topics will build the foundation for future system-oriented testing? These questions and possible approaches will be examined and debated by a panel of experts from industry and academia. |
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14:00 – 15:00 |
Session 9B – Embedded Tutorial: Alternatives to Fault Injections for Early Safety/Security Evaluations (Seminar Room 1)
Organizer and Moderator: Régis Leveugle, TIMA, FR
Presenters:
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16:30 – 22:00 |
Social Event
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30
Thursday
May, 2019
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08:30 – 09:15 |
Keynote 3 (Conference Room 1)
Moderator: Hans-Joachim Wunderlich, University of Stuttgart, DE
Hold the reins in test engineering
Jochen Müller, Bosch, DE
Abstract
The lecture describes recent and upcoming trends in the automotive industry with its derived automotive ASIC requirements and drivers behind. In addition some pitfalls in requirements engineering with respect to customer needs, specifications and test realization are presented. |
09:15 – 10:15 |
Session 11A – Approximate and Neuromorphic Computing (Conference Room 1)
Moderators: Rohit Kapur, Cadence, US, and Adit Singh, Auburn University, US
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Moderator: Pete Harrod, ARM, UK
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Session 11C – Embedded Tutorial: Connecting the Dots: How IEEE P1687.1, P1687.2, and IEEE P2427 Play Together (Seminar Room 1)
Organizer: Martin Keim, Mentor, a Siemens Business, US
Moderator: Jeff Rearick, AMD, US
Presenters:
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10:15 – 11:00 |
Coffee and Poster Session 3 (Foyer 1st Floor)
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11:00 – 12:30 |
Session 12A – DfT and BIST for 3D and AMS (Conference Room 1)
Moderators: Jürgen Alt, Intel, DE, and Erik Jan Marinissen, IMEC, BE
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Moderator: Jürgen Schlöffel, Mentor, a Siemens Business, DE
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Session 12C – Special Session: Dependable Wireless Industrial IoT Networks (Seminar Room 1)
Organizers: Fotis Foukalas and Paul Pop, TU-Denmark, DK
Moderator: Fotis Foukalas, TU-Denmark, DK
Presenters:
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12:30 – 14:00 |
Lunch (Parkpavillon Ground Floor)
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ETS2020 Executive Committee meeting (Seminar Room 4)
Chair: Artur Jutman, Testonica Lab, EE, and Jaan Raik Tallinn University of Technology, EE
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14:00 – 15:30 |
Session 13 – Diagnosis (Conference Room 1)
Moderators: Sybille Hellebrand, University of Paderborn, DE, and Stefan Holst, Kyushu Institute of Technology, JP
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15:30 – 16:00 |
Closing Session (Conference Room 1)
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16:00 – 18:00 | ||
31
Friday
May, 2019
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09:00 – 15:30 | |
09:00 – 10:00 | ||
10:00 – 12:15 | ||
12:15 – 18:00 |