Technical Program Tab

Technical Program

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Monday
May 27, 2019
Tuesday
May 28, 2019
Wednesday
May 29, 2019
Thursday
May 30, 2019
Friday
May 31, 2019
    Keynote 2:
Shaojun Wei

08:30-09:15
Conference Room 1
Keynote 3:
Jochen Müller

08:30-09:15
Conference Room 1
 
Opening
09:00-09:30
Conference Room 1
Fringe
Workshop
TESTA

09:00-15:30
Seminar Room 4
Fringe
Workshop
TruDevice

09:00-10:00
Seminar Room 1
Session
7A
Memory

09:15-10:15
Conference Room 1
Session
7B
Vendor

09:15-10:15
Seminar Room 7/8
Session
7C
Embedded
Workshop

09:15-10:15
Seminar Room 1
Session
11A
AxC &
Neuromorphic

09:15-10:15
Conference Room 1
Session
11B
Vendor

09:15-10:15
Seminar Room 7/8
Session
11C
Embedded
Tutorial 2

09:15-10:15
Seminar Room 1
Keynote 1:
Kaushik Roy

09:30-10:15
Conference Room 1
Fringe
Workshop
Joint
Shiva / TruDevice

10:00-12:15
Seminar Room 1
Coffee
& Posters 1

10:15-11:00
Foyer 1st Floor
Coffee
& Posters 2

10:15-11:00
Foyer 1st Floor
Coffee
& Posters 3

10:15-11:00
Foyer 1st Floor
Session
2A
Security

11:00-12:30
Conference Room 1
Session
2B
Analog &
Mixed Signal
Test

11:00-12:30
Seminar Room 1
Session
2C
ETS2

11:00-12:30
Seminar Room 7/8
Session
8A
Modeling,
Validation &
Verification

11:00-12:30
Conference Room 1
Special
Session
8B
Security in
Autonomous
Systems

11:00-12:30
Seminar Room 7/8
Session
8C
Embedded
Workshop

11:00-12:30
Seminar Room 1
Session
12A
DfT &
BIST for 3D
& AMS

11:00-12:30
Conference Room 1
Session
12B
Vendor

11:00-12:30
Seminar Room 7/8
Special
Session
12C
Dependable
Wireless
IoT

11:00-12:30
Seminar Room 1
Fringe
Workshop
Shiva

12:15-18:00
Seminar Room 1
ETS
Steering Committee
meeting

12:30-14:00
Seminar Room 4
Lunch
12:30-14:00
Parkpavillon Ground Floor
ETS2020
Executive Committee
meeting

12:30-14:00
Seminar Room 4
TSS Monday Tutorials
Part A
  Special
Session
3A
Automotive
Quality

14:00-15:30
Conference Room 1
Session
3B
PhD Contest

14:00-15:30
Seminar Room 1
Session
9A
Panel

14:00-15:30
Conference Room 1
Session
9B
Embedded
Tutorial 1

14:00-15:00
Seminar Room 1
Plenary
Session 13
Diagnosis

14:00-15:30
Conference Room 1
AMS & RF
Test

14:00-16:00
Seminar Room 1
System-Level
Test

14:00-16:00
Seminar Room 7/8
 
Coffee and PhD Forum
15:30-16:15
Closing
15:30-16:00
Conference Room 1
 
Coffee Break ETS
Steering Committee
meeting

16:00-19:00
Seminar Room 4
Fringe
Workshop
TESTA

16:00-18:00
Seminar Room 4
Fringe
Workshop
TruDevice

16:00-18:00
Seminar Room 1
 
Session
4A
Test
Generation

16:15-17:45
Conference Room 1
Session
4B
Fault
Tolerance

16:15-17:45
Seminar Room 1
 
TSS Monday Tutorials
Part B
AMS & RF
Test

16:30-18:30
Seminar Room 1
System-Level
Test

16:30-18:30
Seminar Room 7/8
Break
17:45-18:00
Session 5
Wine &Cheese
Panel

18:00-19:30
Conference Room 1
   
 
 
 


Date Time Event
27
Monday
May, 2019
14:00 – 18:30
Tutorial A (Seminar Room 1)
Analog, Mixed-Signal, RF IC Testing: Essentials and Current Trends
Harlampos Stratigopoulos, Sorbonne University – LIP6, FR

Tutorial B (Seminar Room 7/8)
System-Level Test
Harry Chen, MediaTek, TW

16:00 – 19:00
ETS Steering Committee meeting (Seminar Room 4)
Chair: Matteo Sonza Reorda, Politecnico di Torino, IT

19:00 – 21:00
28
Tuesday
May, 2019
09:00 – 09:30
Opening Session (Conference Room 1)

09:30 – 10:15
Keynote 1 (Conference Room 1)
Cognitive Computing: Design, Verification & Security Challenges
Kaushik Roy, Purdue University, US

10:15 – 11:00
Coffee and Poster Session 1 (Foyer 1st Floor)
  • On the Evaluation of the PIPB Effect within SRAM-based FPGAs
    Corrado De Sio, Sarah Azimi, Luca Sterpone
    Politecnico di Torino, IT
  • B-open: A New Defect in Nanometric Technologies due to SADP Process
    Freddy Forero1, Michel Renovell2, Victor Champac1
    1INAOE, MX, 2LIRMM, FR
  • Test Solutions for High Density 3D-IC Interconnects – Focus on SRAM-on-Logic Partitioning
    Imed Jani, Pascal Vivet, Jean Durupt, Sebastien Thuries, Didier Lattard, Edith Beigne
    CEA-LETI, FR
  • Feature Engineering for Recycled FPGA Detection Based on WID Variation Modeling
    Foisal Ahmed, Michihiro Shintani, Michiko Inoue
    Nara Institute of Science and Technology (NAIST), JP
  • DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs
    Guilherme Cardoso Medeiros1, Mottaqiallah Taouil1, Moritz Fieback1, Leticia Bolzani Poehls2, Said Hamdioui1
    1Delft University of Technology, NL, 2Catholic University of Rio Grande do Sul, BR

11:00 – 12:30
Session 2A – Security (Conference Room 1)
Moderators: Subhasish Mitra, Stanford University, US, and Johanna Sepulveda, TUM, DE
  • Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries
    Dominik Sisejkovic1, Farhad Merchant1, Rainer Leupers1, Gerd Ascheid1, Sascha Kegreiss2
    1RWTH Aachen, DE, 2Hensoldt Cyber GmbH, DE
  • On Integrating Lightweight Encryption in Reconfigurable Scan Networks
    Benjamin Thiemann1, Linus Feiten1, Pascal Raiola1, Bernd Becker1, and Matthias Sauer2
    1University of Freiburg, DE, 2Advantest, DE
  • Revisiting Logic Locking for Reversible Computing
    Nimisha Limaye, Muhammad Yasin, Ozgur Sinanoglu
    New York University Abu Dhabi, AE
Session 2B – Analog and Mixed Signal Test (Seminar Room 1)
Moderators: Hans Kerkhoff, University of Twente, NL, and Haralampos Stratigopoulos, Sorbonne University – LIP6, FR
  • A 52 dB-SFDR 166 MHz Sinusoidal Signal Generator for Mixed-Signal BIST Applications in 28 nm FDSOI technology
    Hani Malloug, Manuel Barragan, Salvador Mir
    TIMA, FR
  • Power Measurement and Spectral Test of ZigBee Transmitters from 1-bit Under-sampled Acquisition
    Thibault Vayssade1, Florence Azaïs2, Laurent Latorre2, Francois Lefevre1
    1NXP, FR, 2LIRMM, FR
  • Model-driven AMS Test Setup Validation Tool prepared for IEEE P1687.2
    Leon van de Logt1, Vladimir Zivkovic2, Ingrid van Baast1
    1D4T Systems, NL, 2Cadence, UK
Session 2C – ETS2: Functional Safety and DFT – Overlap or Conflict? (Seminar Room 7/8)
Moderators: Pete Harrod, ARM, UK, and Zebo Peng, Linkoping University, SE
Presenters:

  • Teresa McLaurin, ARM, US
  • Jan Schat, NXP Semiconductors, DE
  • Michael Schreiner, Infineon, DE

12:30 – 14:00
Lunch (Parkpavillon Ground Floor)

ETS Steering Committee meeting (Seminar Room 4)
Chair: Matteo Sonza Reorda, Politecnico di Torino, IT

14:00 – 15:30
Session 3A – Special Session: Maintaining Automotive Quality for Next Generation Microcontrollers (Conference Room 1)
Organizer and Moderator: Daniel Tille, Infineon Technologies, DE
Presenters:

  • Vladimir Litovtchenko, Synopsys, DE
  • Ralf Arnold, Infineon Technologies, DE
  • Johanna Sepulveda TU-Munich, DE

Session 3B – McCluskey Doctoral Thesis Award Contest – ETS Semi-Finals (Seminar Room 1)
Moderators: Alberto Bosio, École Centrale de Lyon, FR, and Said Hamdioui, TU Delft, NL

15:30 – 16:15
Coffee and PhD Forum (Foyer 1st Floor)
  • A Methodology for Characterization and Mitigation of SET Effects in Combinational Logic
    Marko Andjelkovic, Milos Krstic, Rolf Krämer
    IHP, DE
  • Programmable In-Situ Delay Monitor for Energy-Efficient and Resilient Complex SoC
    Mitko Veleski, Rolf Krämer, Milos Krstic
    IHP, DE
  • Dependability of Safety-Critical Automotive SoC
    Marco Restifo
    Politecnico di Torino, IT
  • A boot-time self-test procedures scheduler for multi-core automotive System-on-Chips
    Andrea Floridia
    Politecnico di Torino, IT
  • Self-Adaptive Cross-Layer Fault Tolerance in Multiprocessor Systems
    Junchao Chen, Milos Krstic
    IHP, DE
  • SAT modulo differential equations
    Tomas Kolarik, Stefan Ratschan
    CTU Prague, CZ
  • Encryption Techniques for Test Infrastructures
    Emanuele Valea1, Marie-Lise Flottes1, Giorgio Di Natale2, Bruno Rouzeyre1
    1LIRMM, FR, 2TIMA, FR
  • On the Evaluation of SET-induced Errors on Dynamically Reconfigurable FPGAs
    Corrado De Sio, Ludovica Bozzoli, Sarah Azimi, Luca Sterpone
    Politecnico di Torino, IT
  • Verifying IEEE 1687 ICL against RTL – Code Coverage and Functional Coverage
    Aleksa Damljanovic
    Politecnico di Torino, IT
  • Efficient hardening solutions on GPUs for safety critical applications
    Fernando Fernandes Dos Santos, Paolo Rech
    Universidade Federal do Rio Grande do Sul, BR
  • Embedded System back-annotation by qualifying component model template
    Katayoon Basharkhah
    University of Tehran, IR
  • Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits
    Thomas Lange1, Aneesh Balakrishnan1, Maximilien Glorieux1, Dan Alexandrescu1, Luca Sterpone2
    1iRoC Technologies, 2Politecnico di Torino, IT
  • Learning Enhanced Diagnosis of Logic Circuit Failures
    Soumya Mittal, Shawn Blanton
    Carnegie Mellon University, US
  • Vector-IR-based translation approach of pattern programs
    Jung-Geun Park, Minsu Kim
    Seoul National University, KR

16:15 – 17:45
Session 4A – Test Generation (Conference Room 1)
Moderators: Grzegorz Mrugalski, Mentor, a Siemens Business, PL, and Melanie Schillinsky, NXP, DE
  • Machine Learning-based Prediction of Test Power
    Harshad Dhotre1, Stephan Eggersgluess2, Krishnendu Chakrabarty3, Rolf Drechsler1
    1University of Bremen, DE, 2Mentor, a Siemens Business, DE, 3Duke University, US
  • On Generating Fault Diagnosis Patterns for Designs with X Sources
    Xijiang Lin1, Sudhakar Reddy2
    1Mentor, a Siemens Business, US, 2University of Iowa, US
  • High-Level Combined Deterministic and Pseudoexhaustive Test Generation for RISC Processors
    Adeboye Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gursoy, Jaan Raik
    Tallinn University of Technology, EE

Session 4B – Fault Tolerance (Seminar Room 1)
Moderators: Valentin Gherman, CEA, FR, and Huang Zhengfeng, Hefei University of Technology, CN
  • IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variations
    Ghazanfar Ali, Jerrin Pathrose, Hans Kerkhoff
    University of Twente, NL
  • STAHL: A Novel Scan-Test-Aware Hardened Latch Design
    Ruijun Ma1, Stefan Holst1, Xiaoqing Wen1, Aibin Yan2, Hui Xu2
    1Kyushu Institute of Technology, JP, 2Anhui University, CN
  • Hardware-Based Aging Mitigation Scheme for Memory Address Decoder
    Daniel Kraak1, Innocent Agbo1, Mottaqiallah Taouil1, Said Hamdioui1, Pieter Weckx2, Stefan Cosemans2, Francky Catthoor2
    1Delft University of Technology, NL, 2IMEC, BE
17:45 – 18:00
Break (Room TBD)

18:00 – 19:30
Session 5: Wine and Cheese Panel: Ask the Experts (Conference Room 1)
Organizer and Moderator: Jeff Rearick, AMD, US

We’ll continue our tradition of tapping the collective expertise of the ETS participants by hosting an interactive “Ask The Experts” session during the Wine and Cheese Panel. The twist is that anyone can ask a question and _everyone_ has the chance to be the expert who answers it (or contests the answer of another expert). The general theme is “The Test Industry Roadmap” but anything goes.  Prizes will be awarded for best question, best answer, and best rebuttal

19:30 – 21:30
29
Wednesday
May, 2019
08:30 – 09:15
Keynote 2 (Conference Room 1)
Moderator: Krishnendu Chakrabarty, Duke University, US
Software Defined Chips: An Innovative Architecture Leading to Intelligent Computing
Shaojun Wei, Tsinghua University, CN
Abstract

Intellectualization is a revolution that human society is experiencing, and it is also the core of the fourth industrial revolution. Obviously it ultimately depends on integrated circuit technology, because not only now, but also in the future for quite a long time, we cannot find other technologies that can replace integrated circuits. Therefore, we have no other options than using integrated circuit technology for implementing intelligence. It is also the reason why people spend a lot of energy focusing on AI chips in the development of artificial intelligence. For a large number of artificial neural networks each of which corresponds to only one application, an integrated circuit that cannot be changed after manufacturing is obviously far from the requirements. Even devices such as FPGA, which are field programmable, can hardly meet the needs of AI development in terms of computing efficiency and energy efficiency. We urgently need to find an innovative chip architecture. This paper will focus on software definition chip (SDC), an innovative chip architecture that allows the chip function to dynamically change in real time with the change of software. SDC moves from traditional software adapting hardware to hardware adapting software. By gradually improving the intelligence of chip, SDC eventually moves to intelligent chip. Besides, the core of SDC is a dynamically reconfigurable PE array that not only has high computing efficiency and energy efficiency, but also improves the reliability of the chip through redundant design, and improve the ability to resist attacks by randomly configuring the space-time position of the sensitive circuits as well. In addition, based on dynamic reconfigurability, the potential security threats caused by test paths in DFT are also mitigated.

09:15 – 10:15
Session 7A – Memory (Conference Room 1)
Moderators: Michele Stucchi, IMEC, BE, and Ioana Vatajelu, TIMA, FR
  • Pinhole Defect Characterization and Modeling for STT-MRAM Testing
    Lizhou Wu1, Siddharth Rao2, Guilherme Cardoso Medeiros1, Mottaqiallah Taouil1, Erik Jan Marinissen2, Farrukh Yasin2, Sebastien Couet2, Said Hamdioui1, Gouri Sankar Kar2
    1Delft University of Technology, NL, 2IMEC, BE
  • A Machine Learning based Approach to Optimize Repair of Embedded Flash Memories in Automotive System-on-Chip
    Andrea Manzini1,3, Pietro Inglese2,4, Leonardo Caldi4, Riccardo Cantoro2, Giambattista Carnevale3, Matteo Coppetta3, Massimo Giltrelli3, Nellina Mautone3, Fernanda Irrera1, Rudolf Ullmann4, Paolo Bernardi2
    1University of Rome, IT, 2Politecnico di Torino, IT, 3Infineon, IT, 4Infineon, DE
Hans Manhaeve, Ridgetop Europe, BE
  • Test and Repair for SoC Memories and Hierarchical Test for AMS & PHY IP
    Yervant Zorian
    Synopsys Fellow, US
  • Advantest and EDA: Partnering to Deliver Customer Values
    Michael Braun
    Advantest, DE

Session 7C – Embedded Workshop: Case Studies (Seminar Room 1)
Moderator: Gildas Leger, IMSE-CNM, ES
  • Flight Safety Certification Implications for Complex Multi-Core Processor based Avionics Systems
    Jyotika Athavale1, Riccardo Mariani2, Michael Paulitsch3
    1Intel Corporation, US, 2Intel Corporation, IT, 3Intel Corporation, DE
  • Hybrid Verification Methodology for Automotive RADAR
    Shiva Negendar, Sainath Karlapalem, Paulraj Kanakaraj, Shashank Venugopal
    NXP, IN
10:15 – 11:00
Coffee and Poster Session 2 (Foyer 1st Floor)
  • Concurrent Estimation of a PLL Transfer Function by Cross-Correlation with pseudo-random Jitter
    Jan Schat, Ulrich Möhlmann
    NXP Semiconductors, DE
  • PaTran: a Translation Platform for Test Pattern Programs
    Jung-Geun Park1, Minsu Kim1, Sungyeol Kim2, Insu Yang2, Hyunsoo Jung2, Soo-Mook Moon1
    1Seoul National University, KR, 2Samsung Electronics Co., Ltd., KR
  • A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks
    Michele Portolan1, Riccardo Cantoro2, Ernesto Sanchez2
    1TIMA, FR, 2Politecnico di Torino, IT
  • Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme
    Mahsa Akhsham, Atefesadat Seyedolhosseini, Zainalabedin Navabi
    University of Tehran, IR
  • Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns
    Sebastian Huhn1, Daniel Tille2, Rolf Drechsler3
    1DFKI GmbH, DE, 2Infineon, DE, 3University of Bremen/DFKI, DE

11:00 – 12:30
Session 8A – Modeling, Validation and Verification (Conference Room 1)
Moderators: Bernd Becker, University of Freiburg, DE, and René Krenz-Baath, Hamm-Lippstadt University of Applied Sciences, DE
  • Back-Annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling
    Zainalabedin Navabi, Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah
    University of Tehran, IR
  • Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks
    Aleksa Damljanovic1, Artur Jutman2, Giovanni Squillero1, Anton Tsertov2
    1Politecnico di Torino, IT, 2Testonica Lab, EE
  • Exploring Algebraic Interpolants for Rectification of Finite Field Arithmetic Circuits with Groebner Bases
    Utkarsh Gupta1, Priyank Kalla1, Irina Ilioaea2, Florian Enescu2
    1University of Utah, US, 2Georgia State University, US
Session 8B – Special Session: Security in Autonomous Systems (Seminar Room 7/8)
Organizer and Moderator: Ilia Polian, University of Stuttgart, DE
Presenters:

  • Francesco Regazzoni, University of Lugano, CH
  • Marc Stöttinger, Continental AG, DE
  • Stefan Katzenbeisser, TU-Darmstadt, DE

Session 8C – Embedded Workshop: Advances in DfT (Seminar Room 1)
Moderator: Jochen Rivoir, Advantest, DE, Matthias Sauer, Advantest, DE
  • Architecture for fast and precise and Voltage Measurement for Analog Test Points
    Jan Schat
    NXP Semiconductors, DE
  • Facilitating Memory Test Using Shared Bus Interface
    Albert Au1, Sebastian Bromberek2, Martin Keim3 Benoit Nadeau-Dostie1, Artur Pogiel2
    1Mentor, a Siemens Business, CA, 2Mentor, a Siemens Business, PL, 3Mentor, a Siemens Business, US
  • Novel Clock and Reset DFT Methods to Improve Hierarchical ATPG Pattern Reuse Shown on a GPU Design
    Beomseok Shin2, Jinsoo Park2, Jungyul Pyo2, Youngmin Shin2, Ron Press1, Takeo Kobayashi1, Yoon Dong Lee3, Inchul Kim3
    1Mentor, a Siemens Business, US, 2Samsung Electronics, KR, 3Mentor, a Siemens Business, KR
12:30 – 14:00
Lunch (Room TBD)

14:00 – 15:30
Session 9A – Panel: System-level Test (SLT) – What does the Future Hold? (Conference Room 1)
Organizer: Harry Chen, MediaTek, TW
Panelists:

  • John Yi, AMD, US
  • Marc Hutner, Teradyne, CA
  • Anil Bhalla, Advantest, US
  • Carsten Ohlhoff, Continental Automotive, DE
  • Adit Singh, Auburn University, US
  • Paolo Bernardi, Politecnico di Torino, IT
 Summary:

Testing of complex electronics-based systems is becoming more difficult and costly. To meet the challenge, can we count on enhanced structural test using advanced fault models such as cell-aware? Or do we have to employ more system-level test (SLT)? Can a more methodical and standardized approach to SLT over current ad hoc practices be developed to achieve better cost efficiency? What about balancing the roles of traditional ATE and SLT testers for a more optimal test flow. Perhaps bring more SLT content upstream to wafer probe or include structural test content as part of in-system test? Is end-to-end test data analytics the solution to closing the diagnostic loop to identify the root causes of field failures? Should we be paying more attention to the role of embedded software when modern complex systems fail? What academic research topics will build the foundation for future system-oriented testing? These questions and possible approaches will be examined and debated by a panel of experts from industry and academia.

14:00 – 15:00
Session 9B – Embedded Tutorial: Alternatives to Fault Injections for Early Safety/Security Evaluations (Seminar Room 1)
Organizer and Moderator: Régis Leveugle, TIMA, FR
Presenters:

  • Régis Leveugle, TIMA, FR
  • Michele Portolan, TIMA, FR
  • Stefano di Carlo, Politecnico di Torino, IT

16:30 – 22:00
30
Thursday
May, 2019
08:30 – 09:15
Keynote 3 (Conference Room 1)
Moderator: Hans-Joachim Wunderlich, University of Stuttgart, DE
Hold the reins in test engineering
Jochen Müller, Bosch, DE
Abstract

The lecture describes recent and upcoming trends in the automotive industry with its derived automotive ASIC requirements and drivers behind. In addition some pitfalls in requirements engineering with respect to customer needs, specifications and test realization are presented.
A supporting toolset is discussed to achieve a continuous flow and control of requirements starting with the customer specification, followed by datasheet and ending in testing software. As an example, an eclipse based toolchain is presented with dedicated features for requirements control including automatic code generation of test programs out of this tool. This code supports efficient installation and execution on selected modern test systems.

09:15 – 10:15
Session 11A – Approximate and Neuromorphic Computing (Conference Room 1)
Moderators: Rohit Kapur, Cadence, US, and Adit Singh, Auburn University, US
  • Approximate computing design exploration through data lifetime metrics
    Alessandro Savino1, Michele Portolan2, Régis Leveugle2, Stefano Di Carlo1
    1Politecnico di Torino, IT, 2TIMA, FR
  • Impact of Reduced Precision in the Reliability of Deep Neural Networks for Object Detection
    Fernando Fernandes Dos Santos, Philippe Navaux, Luigi Carro, Paolo Rech
    Universidade Federal do Rio Grande do Sul, BR
Moderator: Pete Harrod, ARM, UK
  • Mini-Tutorial: The (black) art of current test
    Hans Manhaeve, CEO Ridgetop Europe, BE

Session 11C – Embedded Tutorial: Connecting the Dots: How IEEE P1687.1, P1687.2, and IEEE P2427 Play Together (Seminar Room 1)
Organizer: Martin Keim, Mentor, a Siemens Business, US
Moderator: Jeff Rearick, AMD, US
Presenters:

  • Martin Keim, Mentor, a Siemens Business, US
  • Jeff Rearick, AMD, US
  • Vladimir Zivkovic, Cadence, UK
10:15 – 11:00
Coffee and Poster Session 3 (Foyer 1st Floor)
  • Test Pattern Generator for Majority Voter based QCA Combinational Circuits targeting MMC Defect
    Vaishali Dhare, Usha Mehta
    Nirma University, IN
  • Symbolic Circuit Analysis under an Arc Based Timing Model
    Goerschwin Fey1, Alberto Garcia-Ortiz2
    1TU Hamburg, DE, 2University of Bremen, DE
  • A Dynamic Greedy Test Scheduler for Optimizing Probe Motion in In-Circuit Testers
    Matteo Sonza Reorda1, Giovanni Squillero1, Luciano Bonaria2, Maurizio Raganato2
    1Politecnico di Torino, IT, 2SPEA, IT

11:00 – 12:30
Session 12A – DfT and BIST for 3D and AMS (Conference Room 1)
Moderators: Jürgen Alt, Intel, DE, and Erik Jan Marinissen, IMEC, BE
  • Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection
    Mehmet Ince, Sule Ozev
    Arizona State University, US
  • Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs
    Arjun Chaudhuri1, Sanmitra Banerjee1, Heechun Park2, Bon Woong Ku2, Krishnendu Chakrabarty1, Sung Kyu Lim2
    1Duke University, US, 2Georgia Institute of Technology, US
  • K^3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-Multiplexing
    Panagiotis Georgiou, Iakovos Theodosopoulos, Chrysovalantis Kavousianos
    University of Ioannina, GR
Moderator: Jürgen Schlöffel, Mentor, a Siemens Business, DE
  • Moving DFT solutions to the next level
    Kan Thapar
    Mentor, a Siemens Business, UK
  • IP Solutions for Functional Safety Applications
    Pete Harrod
    Director of Functional Safety, CPU Group, ARM, UK
  • ProChek Plus – A solution for Process assessment from a quality/reliability perspective
    Hans Manhaeve
    CEO Ridgetop Europe, BE

Session 12C – Special Session: Dependable Wireless Industrial IoT Networks (Seminar Room 1)
Organizers: Fotis Foukalas and Paul Pop, TU-Denmark, DK
Moderator: Fotis Foukalas, TU-Denmark, DK
Presenters:

  • Fabrice Theoleyre, CNRS, FR
  • Carlo Alberto Boano, TU-Graz, AT
  • Chiara Buratti, University of Bologna, IT
  • Fotis Foukalas, TU-Denmark, DK
12:30 – 14:00
Lunch (Parkpavillon Ground Floor)

ETS2020 Executive Committee meeting (Seminar Room 4)
Chair: Artur Jutman, Testonica Lab, EE, and Jaan Raik Tallinn University of Technology, EE

14:00 – 15:30
Session 13 – Diagnosis (Conference Room 1)
Moderators: Sybille Hellebrand, University of Paderborn, DE, and Stefan Holst, Kyushu Institute of Technology, JP
  • A Supervised Machine Learning Application in Volume Diagnosis
    Yue Tian1, Gaurav Veda2, Wu-Tung Cheng2, Manish Sharma2, Huaxing Tang2, Neerja Bawaskar3, Sudhakar Reddy1
    1University of Iowa, US, 2Mentor, a Siemens Business, US, 3Globalfoundries, US
  • Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution
    Yu Huang, Jakub Janicki, Szczepan Urban
    Mentor, a Siemens Business, US
  • LearnX: A Hybrid Deterministic-Statistical Defect Diagnosis Methodology
    Soumya Mittal, Shawn Blanton
    Carnegie Mellon University, US

15:30 – 16:00
Closing Session (Conference Room 1)

16:00 – 18:00
31
Friday
May, 2019
09:00 – 15:30
09:00 – 10:00
10:00 – 12:15
12:15 – 18:00