Stefano Di Carlo is an associate professor in the department of Control and Computer Engineering at Politecnico di Torino (Italy) since 2014. He holds a Ph.D. (2003) and an M.S. equivalent (1999) in Computer Engineering and Information Technology from the Politecnico di Torino in Italy. Di Carlo’s research contributions include Reliability Analysis, FPGA Design, Memory Testing, Reliability analysis of NVM memories with ECC, Design for Testability, Built-In Self-Test, Fault Simulation and Automatic Test Generation.
He has been part of the program and organizing committee of several IEEE and ACM conferences and he is member of the Editorial Board of Springer Journal of Electronic Testing: Theory and Applications. He served as reviewer of the IEEE Transactions on Computers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on VLSI, IEEE Software, and several other IEEE/ACM journals.
He coordinated the FP7 CLERECO project. Di Carlo is a Senior Member of the IEEE, and a Golden Core Member of the IEEE Computer Society. His research interests include Reliability, Memory Testing and BIST.
Email: stefano.dicarlo@polito.it
Phone: 011-090-7080, Fax: 011-090-7099
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https://orcid.org/0000-0002-7512-5356