We received today an very good news. After more than 1 year from its end, the FP7 Clereco project (http://www.clereco.eu) still produces results in the field of cross-layer reliability analysis.

A paper has been accepted for publication in an upcoming issue of IEEE Transactions on Computers proposing a cross-layer multi-objective design space exploration algorithm developed to help designers when building soft error resilient electronic systems.

We just got the good news that our paper “Trading-off reliability and performance in FPGA-based reconfigurable heterogeneous systems” has been accepted for an oral presentation at the 13th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era.