Author: Stefano Di Carlo
Testgroup @ HiPEAC CSW 2019
Probabilistic estimation of the application-level impact of precision scaling in approximate computing applications @ Microelectronics Reliability Journal
Paper accepted @ DFTS 2019
On behalf of the DFT19 Program Committee, we are delighted to inform you that your paper “Combining Cluster Sampling and ACE analysis to improve fault-injection based reliability evaluation of GPU-based systems” has been ACCEPTED for ORAL presentation at the 32th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
Invited talk @ 25th IEEE International Symposium on On-Line Testing and Robust System Design
Today at 5:15PM I’m going to give an invited talk at the 25th IEEE International Symposium on On-Line Testing and Robust System Design in Kazan in Rhodes (Greece).
The topic of the talk will be “Bayesian Models For Early Cross-Layer Reliability Analysis and Design Space Exploration” and will be part of Session 5S “Cost-Effective Resilience: Advanced Cross-Layer Analysis and Optimization Techniques” organized by Prof. M. Shafique (TU Wien).
SyRA Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems @ IEEE Transactions on Computer
After more than 1 year from its end, the FP7 Clereco project (http://www.clereco.eu) still produces results in the field of cross-layer reliability analysis.
This paper that has been accepted for publication in an upcoming issue of IEEE Transactions on Computers proposes a framework for Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.