This project focuses on the problem of automating the definition of new memory fault models using layout and electrical simulations.
- Duration: 2009-2011
- Coordinator: Politecnico di Torino
- Partners: Politecnico di Torino, Universitat Politecnica de Catalunya (UPC)
- Funded by: Italian Ministry of Foreign Affairs
The continuous scaling of circuit technology enables the integration of complete systems and even complete computer clusters on a single die (System-on-Chip SoC). At the same time, Very Deep Sub-Micron (VDSM) devices are exposed to a growing number of defect mechanisms due to an increased sensitivity to environmental influences. The “International Technology Roadmap for Semiconductors” estimates that by 2019 only between 10% and 20% of chips will be defect free. SoCs are rapidly moving from logic dominant chips to memory dominant devices with up tp 90% of silicon area used by memories. Embedded memories need to be deeply tested and must include repair capabilities to ensure/enhance an optimal yield level. The success of next generation SoCs will strongly depend on the ability of establishing new fault models that efficiently represent physical defects introduced by VDSM technologies and, designing of optimal test/diagnosis algorithms to guarantee high defect coverage and to reduce the defects-per-million level.
Nowadays, this type of activity is mainly performed manually. Nevertheless, the complexity of VDSM technologies makes the definition of functional fault models a non-trivial task. This project focuses on the problem of automating the definition of new memory fault models using layout and electrical simulations.
The methodology used to reach the proposed goal will rely on the analysis of the main sources of defects in modern memory devices, and on the analysis of the state-of-the-art techniques used to analyze the effects of these defects. The outcome of this analysis will represent the basis for the identification of the requirements needed to build efficient automation approaches that may help test engineers in working with future technologies.
In particular, in a first phase of the project the main goal will be the evaluation of the impact of resistive, capacitive and mixed defects on memory devices produced using VDSM technologies (i.e., 65nm, 46nm, 32nm, 22nm). The evaluation, performed by means of layout and electrical simulations will not be limited to standard memory architectures, but will include low-power memories and cache memories.
Information collected during the first phase will represent the basis of the second phase whose goal is the implementation of software instruments able to automate and to support test engineers in the identification of new fault models and in the design of efficient memory test algorithms. In this phase, different algorithmic approaches (e.g., evolutive programming, neural networks, etc.) able to solve complex problems will be investigated, trying to identify the solution with higher efficiency. Project results, will be relevant for the academic community as well as for the potential wide industrial application.
The project results will be made available to the scientific community through publications co-authored by Politecnico di Torino and Universitat Politecnica de Catalunya, to be submitted to the main international conferences and scientific journals in the field of digital systems design and test.