The purpose of this project is the integration of a new memory technology into the widely used memory simulator CACTI.

The target technology is STT-MRAM, one of the most promising magnetic technologies up to now. It will be probably available on the market by the end of this decade.

CACTI has been chosen because it is an open source high-level simulator, widely known in academic research field. It gives fast but accurate predictions about timing performance, occupied area, power consumption.


Stefano Arcaro and Diego Pala, master students under the supervision of:

Marco Indaco

How to cite STT-CACTI

The STT-CACTI development team  has invested a lot of time and effort in creating STT-CACTI as it is today. Please give credit where credit is due and cite RASTA when you use it for your research activities.

STT-CACTI can be cited through this papers:

S. Arcaro, S. Di Carlo, M. Indaco, D. Pala, P. Prinetto and E. I. Vatajelu, “Integration of STT-MRAM model into CACTI simulator,” 2014 9th International Design and Test Symposium (IDT), Algiers, 2014, pp. 67-72.
doi: 10.1109/IDT.2014.7038589


author={S. Arcaro and S. Di Carlo and M. Indaco and D. Pala and P. Prinetto and E. I. Vatajelu},
booktitle={Design Test Symposium (IDT), 2014 9th International},
title={Integration of STT-MRAM model into CACTI simulator},
keywords={MRAM devices;cache storage;integrated circuit design;integrated circuit reliability;low-power electronics;CACTI simulator;SRAM;STT-MRAM macro design;cell level;energy consumption;high-performance memories;low-power cache memories;memory system designers;memory technologies;microlevel design choices;reliability;spin-transfer torque magnetic random access memory;system-level tool;Arrays;Cache memory;Magnetic tunneling;Random access memory;Resistance;Switches;Transistors;CACTI;Emerging Memories;STT-MRAM},


STT-CACTI source code from TestGroup SVN Repository

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