This research addresses the problem of defining new techniques to improve the quality and dependability of complex digital systems a.k.a. System-on-Chip (SoCs).
- Duration: 2000-2006
- Coordinator: Politecnico di Torino
- Partners: Politecnico di Torino, LIRMM, UPC, LogicVision, Virage Logic, Siemens ICN
- Funded by: Istituto superiore Mario Boella
- www: http://www.testgroup.polito.it/tdoc/
The main characteristic of SoC is that they integrate in a single digital chip all the components that historically were placed on a hardware board.
These high-integrated devices can run incredibly faster than old digital boards (and are also considerably cheaper), but, since the direct access to the different components (called cores) is impossible, their test is currently a major industrial challenge, from both a technical and an economical point of view. Exploiting the expertises of three well known European universities and three major companies (located one in Europe and two in the USA, respectively), the research aims at defining new Design for Testability (DfT), Built-In Self-Test (BIST), and Built-In Self-Repair (BISR) techniques to improve the quality and dependability of System-on-Chip (SoCs), while concurrently reducing their testing cost.The main results expected from this research can be categorized in three different classes: Innovative techniques for BIST, Self Repair, and Dependability improvement in SoCs. Each of the mentioned fields will constitute a separate milestone in the project evolution. Two real industrial test cases embedding all of the mentioned techniques, in order to show the applicability of the results, their usefulness, and their impacts, from both an industrial and a social point of view. A set of high-level scientific publications in the proceedings of the main international conferences and technical journals and magazines.All milestones and results will be “validated” against their technical content and industrial relevance by a steering committee and an industrial committee.