Paper accepted @ DTIS 2018

Recent years have witnessed the rapid growth of heterogeneous systems, composed of CPUs and hardware accel- erators, to face up the constant increase of computational perfor- mance demand of digital systems. In this scenario, FPGAs offer the possibility to implement high performance reconfigurable accelerators, able to speed up the intrinsically parallel portions of applications. The study of reconfigurable heterogeneous systems is still maturing and, while some contributions about performance and power consumption are available, in literature there are few works addressing reliability.

This paper that will be presented at the 13th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2018) analyzes reconfigurable heterogeneous systems in presence of permanent faults occurring in the FPGA. In this context, a reconfigurable heterogeneous architecture, including a Run Time Manager responsible for the communication of software tasks and the FPGA, the scheduling and the placement of hardware tasks, is presented. In addition, the paper introduces a reconfigurable heterogeneous system simulator for the proposed architecture. This simulator is able to evaluate during the design phase the degradation of the system performance due to permanent faults and allows to efficiently explore the design space dimensions.

Alessandro Vallero, Alberto Carelli and Stefano Di Carlo  “Trading-off reliability and performance in FPGA-based reconfigurable heterogeneous systems” 13th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2018), April 10-12, 2018, Taormina, Italy