Paper accepted @ DSN 2017

Reliability assessment has always been a major concern in the design of computing systems. The results of the assessment highlight and guide enhancements which trigger re-design cycles; thus early and accurate reliability assessment is of profound importance. For the purposes of early reliability analysis, abstract models of the design (which are available in early design stages) are typically used. These models, however, may not be completely accurate compared to the actual final design. Existing literature has not quantified this inaccuracy, through a comparison between Register-Transfer-Level (RTL) and microarchitecture-level reliability assessment on the same commercial microprocessor design.

In this new paper that will be presented at the 47th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2017) on June 26-29, 2017 in Denver, we present reliability assessment using statistical fault-injection on the RTL and Microarchitectural models of the same commercial ARM Cortex-A9 processor. The assessment was performed using the same benchmark workloads and equivalent configurations of the hardware structures. The results show that, compared to RTL model, the almost 200x faster microarchitectural model reports an average difference of 0.7 percentile units (10%) on the vulnerability estimation of register file and 3 percentile units (20%) on the vulnerability estimation of L1 data cache.


Stefano Di CARLO





Paper Info:

Athanasios Chatzidimitriou*, Manolis Kaliorakis*, Dimitris Gizopoulos*, Maurizio Iacaruso†, Mauro Pipponzi†, Riccardo Mariani†, Stefano Di Carlo§, “RT Level vs. Microarchitecture Level Reliability Assessment: Case Study on ARM Cortex-A9 CPU“, 47th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2017), June 26-29, 2017 in Denver, CO (USA).

* University of Athens, {achatz | manoliskal | dgizop}
† Yogitech1, {maurizio.iacaruso | mauro.pipponzi | riccardo.mariani}
§ Politecnico di Torino,

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